GOWIN FPGA exact-MPN engineering and sourcing guide
GW5AST-LV138PG484AC1/I0: Package, Design Checks, and Sourcing
GW5AST-LV138PG484AC1/I0 is a GOWIN Arora V GW5AST-138 device in the PG484A/PBGA-484 package class. An accessible GOWIN order-code reference maps LV to a 0.9 V or 1.0 V core-supply option, 138 to the 138.24K-LUT density, and PG484A to a 1.0 mm-pitch PBGA-484 package. The complete C1/I0 suffix, package-specific I/O availability, pinout, power rails, configuration mode, documentation revision, traceability requirement and lifecycle status still require a current-source check.
This is a verification guide, not an inventory promise. The exact query is product-led commercial intent, so the finished destination should be an exact model page with a quote handoff rather than a generic FPGA blog. This draft does not establish Apex stock, price, lead time, authorization or an approved replacement.
Quick decision: what can be used now and what must be reconfirmed
| Decision area | Evidence-supported conclusion | Check before BOM release or RFQ |
|---|---|---|
| Manufacturer and family | The exact MPN is listed by an independent product catalogue as GOWIN, and GOWIN documents GW5AST-138 as an Arora V FPGA family member. | Record the requested manufacturer and complete MPN exactly as written, including the slash suffix. |
| Package | The exact listing says PBGA-484. GOWIN identifies PG484A as PBGA484 with 1.0 mm pitch and a 23 x 23 mm body. | Use the current GOWIN package-and-pinout document plus the released PCB footprint; do not reuse a generic 484-ball footprint. |
| Logic density and core voltage | An accessible GOWIN order-code reference maps 138 to 138.24K LUTs and LV to 0.9 V or 1.0 V core supply. | Confirm the active data sheet, power tree and sequencing for the exact board revision. |
| Grade suffix C1/I0 | An older official production-code explanation explicitly uses C1/I0 and explains the commercial/industrial speed relationship. | Confirm the current DS1239 definition, required operating temperature, screening or traceability documents and customer acceptance rule. |
| Interfaces and I/O | GW5AST-138 family resources are not all available in every package. A current GOWIN overview lists PG484A with four transceivers and no MIPI D-PHY entry. | Validate the exact pinout, bonded interfaces and package-specific I/O count before routing high-speed or MIPI interfaces. |
Decode the part number without overclaiming
The public GOWIN DS1104-1.0E document is an accessible older reference, while GOWIN’s current documentation index lists DS1239 version 1.0.3E as the newer GW5AST data sheet. DS1104 is useful for explaining the visible code; DS1239 and the current package-and-pinout guide take precedence for a production decision.
| MPN section | Meaning supported by the accessible GOWIN reference | Practical implication |
|---|---|---|
| GW5AST | Arora V GW5AST product series. The current GOWIN family page identifies GW5AST as the RISC-V AE350 variant. | Do not substitute a different GW5A, GW5AS, GW5AT or GW5ART prefix merely because the ball count looks similar. |
| LV | DS1104 defines LV as 0.9 V or 1.0 V core supply. | A board must derive its rail plan from current electrical documentation, not from a shorthand label alone. |
| 138 | DS1104 defines 138 as 138.24K LUTs. | This is a capacity identifier, not a complete statement of package-specific I/O, transceiver or hard-IP availability. |
| PG484A | DS1104 identifies PG484A as PBGA484 with 1.0 mm pitch. | Confirm the pad map, ball A1 orientation, escape routing, solder-mask strategy and assembly constraints against the current package guide. |
| C1/I0 | DS1104 describes C as commercial, I as industrial, and 0, 1 and 2 as relative speed grades; it specifically discusses paired codes such as C1/I0. | Treat this as a grade-and-speed verification task. It does not authorize one universal temperature or timing claim in an RFQ. |
The same DS1104 revision says that paired commercial/industrial grades are screened to industrial standards and gives 85 C commercial and 100 C industrial maximum temperatures in that older reference. Because the current family data sheet is DS1239, retain this only as an ordering-code clue. Obtain the current data sheet, manufacturer confirmation and the customer’s actual temperature requirement before calling a received lot commercial or industrial for a released project.
Family resources: useful for screening, not a substitute for the exact data sheet
GOWIN’s Arora V family page lists the following GW5AST-138 resources. They are family-level screening data. Package, grade, voltage, speed, configuration and design conditions can limit what a particular implementation may use.
| Family-level resource | GOWIN value | What the value does and does not tell a buyer |
|---|---|---|
| LUT4 and registers | 138,240 LUT4; 138,240 registers | Confirms the 138-class fabric level. It does not confirm timing closure for a design. |
| On-chip memory | 1,080 kb shadow SRAM and 6,120 kb block SRAM across 340 BSRAM blocks | Start resource planning here, then validate memory mode, clocking and actual synthesis utilization. |
| DSP and clocking | 298 DSP blocks; up to 12 PLLs; 16 global clocks; 24 high-speed clocks | Up-to values are not a package- and grade-specific timing guarantee. |
| Hard processor | RISC-V AE350_SOC | Establishes that the GW5AST family includes a hard processor. It does not define a boot architecture, software image, security configuration or system validation plan. |
| Family high-speed resources | Up to 8 transceivers; the family page lists a 270 Mbps to 12.5 Gbps transceiver range | Do not apply a family maximum to the PG484A implementation without current package-specific documentation and channel-loss conditions. |
| Core-voltage family value | 0.9 V or 1.0 V typical family options | Treat this as the beginning of power-tree design, not a complete VCC, VCCIO, analog-rail or ramp-rate specification. |
The GOWIN family page also shows DDR3, LVDS, PCIe and MIPI capabilities for GW5AST-138. These features belong in an engineering requirements review, not in a broad claim that every interface is available. The package is a real constraint.
Why PG484A changes the design conversation
The exact part-number cross-check identifies PBGA-484, while GOWIN’s PG484A package reference identifies a 23 x 23 mm, 1.0 mm-pitch PBGA-484 option. GOWIN’s current Arora V overview lists PG484A as a wire-bond PBGA package with four transceivers and no MIPI D-PHY hard-core entry in that package row. A family-level eight-transceiver or MIPI statement must therefore not be copied into a PG484A board specification.
| Source | PG484A user-I/O statement | Safe use |
|---|---|---|
| GOWIN Arora V overview and older DS1104 resource table | 297 user I/O, with 143 true-LVDS pairs shown in parentheses | Use as historical or family planning context only. |
| GOWIN UG1102-1.0.8E package-and-pinout search extract | 287 user I/O, with 143 true-LVDS pairs shown in parentheses | Treat the difference as a release blocker until the current DS1239 and UG1102 pinout is matched to the exact ordered MPN. |
This discrepancy is not proof that either source is wrong. It is evidence that revision control matters. A released constraint file, schematic symbol and PCB escape strategy must follow current, exact package documentation rather than a copied marketplace attribute or an older overview table.
Board-level checks before you call it a drop-in
GOWIN’s current GW5AT/GW5AST schematic manual lists major supply groups used by the GW5AST family: FPGA core, auxiliary and I/O-bank rails, plus SerDes and MIPI-related rail groups where applicable. It also directs the reader to package-specific pinout data for supply requirements. That creates a practical review sequence:
- Lock the exact source set. Save the current DS1239, UG1102, pinout file and programming/configuration guide with the board revision. If access is gated, obtain them through the manufacturer or authorized support channel before engineering approval.
- Validate every power rail and sequence. Check core, auxiliary, I/O-bank and any enabled high-speed interface rails. Do not infer a complete power tree from LV or from a family marketing table.
- Bind the symbol to the current pinout. Confirm ball map, bank assignments, dedicated clocks, configuration pins, JTAG, DDR, MIPI or SerDes candidates and no-connect rules.
- Check package-specific interface availability. For PG484A, validate the number of bonded transceivers and the absence or presence of MIPI hard IP in the current source, not the family maximum.
- Choose and validate configuration mode. The current schematic manual lists JTAG, MSPI, SSPI, master/slave serial and master/slave CPU modes for GW5AST-138 PG484A. External flash, pulls, configuration-clock integrity and reset behavior still require board-level verification.
- Close timing at the requested grade. C1/I0 cannot be converted into a universal clock rate. Use the active grade, constraints, PVT conditions and current timing model.
- Plan assembly and inspection. A PBGA-484 part needs a verified land pattern, reflow profile, paste and X-ray or inspection plan appropriate to the contract manufacturer’s process. Do not copy MSL, bake, shelf-life or inspection requirements from a marketplace page into a customer commitment without applicable manufacturer documentation.
For a useful contrast in sourcing discipline, read ApexComponent’s XC7Z020 SoC FPGA sourcing guide. It is not an alternative to this GOWIN part; it illustrates why a processor-plus-programmable-logic family must be sourced by full order code, package, speed and board requirements.
Sourcing: what an RFQ must contain
The query has exact-MPN commercial intent, so the conversion action should be a validation-oriented RFQ. A buyer should provide the following information:
| RFQ field | Why it matters |
|---|---|
| Full MPN: GW5AST-LV138PG484AC1/I0 | Prevents the family root, package and C1/I0 suffix from being silently shortened. |
| Manufacturer requirement: GOWIN | Avoids an unapproved cross-brand or family substitution. |
| Required grade and operating temperature | Separates a customer’s actual environmental requirement from an old code-decoding assumption. |
| Package and board revision | Confirms that PBGA-484 and PG484A are the intended land pattern, not simply a generic 484 BGA. |
| Quantity, target date and traceability requirement | Lets the seller return current availability, price, lead time, provenance and lot information as an RFQ response rather than a static article claim. |
| Documentation revision | Ensures DS1239, UG1102 and the relevant pinout are aligned with the BOM and constraints. |
| Alternate rule | State exact MPN only unless engineering has already supplied a written, testable alternate-approval process. |
Need an exact-MPN FPGA verification request?
For broad catalogue discovery, use the FPGA category. For an exact-MPN verification request, use Contact Us and include the fields above. The contact route is a confirmation handoff; it does not establish live stock, price, lead time, authorization, lifecycle, compliance status or replacement compatibility.
Frequently asked questions
Is GW5AST-LV138PG484AC1/I0 a GOWIN FPGA?
Yes. The exact MPN is independently listed as GOWIN, and the GW5AST-138 family is documented by GOWIN as part of the Arora V FPGA line. Confirm the complete MPN and document revision before ordering.
What package does GW5AST-LV138PG484AC1/I0 use?
The exact listing identifies PBGA-484. GOWIN’s PG484A package reference identifies PBGA484 with 1.0 mm pitch and a 23 x 23 mm body. Use the latest GOWIN package and pinout file, not this article, for the released footprint and ball map.
What does C1/I0 mean on this GOWIN part number?
An accessible older GOWIN data sheet explains C as commercial, I as industrial, and the digit as a relative speed grade; it explicitly discusses paired codes such as C1/I0. Because DS1239 is the current data sheet, verify the current definition, temperature need and lot documentation before treating it as a final qualification statement.
Does PG484A expose every GW5AST-138 interface?
No. The GW5AST-138 family has package-dependent resources. GOWIN’s current overview lists PG484A with four transceivers and no MIPI D-PHY entry, so package-specific pinout and interface checks are mandatory.
Is another 484-ball FPGA a drop-in replacement?
No. Ball count alone does not prove pinout, power rails, configuration, hard IP, I/O bank, timing, PCB escape, firmware or qualification compatibility. Treat any cross-reference as an engineering validation project unless it is already approved for the exact board.
Source and review boundary
Reviewed September 23, 2026. GOWIN’s documentation index lists DS1239, GW5AST series of FPGA Products Data Sheet, version 1.0.3E, released August 14, 2026. The downloadable current source was not publicly retrievable in this research session, so the accessible older DS1104 PDF is used only where it explicitly explains part naming and is labelled as such. The current DS1239, UG1102 package-and-pinout source, exact pinout and manufacturer confirmation take precedence for engineering release and purchasing.
This article does not assert inventory, price, lead time, allocation, authorization, lifecycle, RoHS or REACH status for the exact ordered lot, export classification, certificate status, inspection requirement or an approved alternative. Those items belong in a current supplier/manufacturer response and the released BOM process.