SAR ADC Explained: How Successive Approximation Converters Work

A SAR ADC, or successive approximation register analog-to-digital converter, converts an analog input into a digital code by making a sequence of bit decisions. Instead of checking every possible output code, it uses a binary-search process: test a midpoint, keep or clear the bit based on the comparator result, then repeat with the next bit.

This architecture is widely used because it combines low latency, deterministic conversion timing, useful precision, moderate-to-high throughput, and good power efficiency. SAR ADCs are common in industrial data acquisition, sensor interfaces, control loops, battery-powered instruments, multiplexed measurement systems, and embedded electronics.

What Is a SAR ADC?

A SAR ADC is an analog-to-digital converter that uses a successive approximation register to find the digital code corresponding to a sampled analog input. It starts with the most significant bit (MSB), then works toward the least significant bit (LSB).

For a 12-bit converter, the core algorithm makes 12 main bit decisions. A 16-bit device makes 16. Real devices also need acquisition time, internal settling time, conversion-clock cycles, and digital-interface time. Some products add calibration, averaging, oversampling, or digital filtering, so the complete timing must always be checked in the datasheet.

If you need a broader introduction before comparing ADC architectures, see How Does an Analog-to-Digital Converter Work?.

Main Blocks Inside a SAR ADC

The exact circuit varies by manufacturer and device family, but a conventional SAR ADC contains the following functional blocks:

How Does a Successive Approximation ADC Work?

A SAR conversion can be understood as a controlled binary search. During acquisition, the input sampling network charges to the analog input. The converter then holds that sampled value while the SAR logic and internal DAC test candidate codes.

1. Acquire the input. The sampling capacitor or capacitor array charges toward the input voltage.
2. Start with the MSB. The SAR logic sets the MSB to 1, creating a midscale trial.
3. Generate a trial level. The internal DAC produces the analog level associated with that candidate code.
4. Compare. The comparator determines whether the sampled input is above or below the trial threshold.
5. Keep or clear the bit. The SAR logic retains the bit if the decision requires it, otherwise it clears the bit.
6. Move to the next bit. The next lower bit is tested while the already-decided bits stay fixed.
7. Finish at the LSB. After the last decision, the register contains the final digital code.

Worked Example: 4-Bit SAR Binary Search

Assume an ideal 4-bit unipolar SAR ADC with an input span of 0 to VREF, and let the sampled input be approximately 0.625 × VREF. There are 16 possible codes.

Final ideal code = 1010₂ = 10₁₀

This example is idealized. Real ADC code transitions are affected by offset, gain error, INL, DNL, reference error, noise, and the exact coding scheme. Always use the transfer-function definitions in the device datasheet for production calculations.

Sample-and-Hold and Acquisition Time

The input of a conventional SAR ADC often behaves like a switched-capacitor load. When the sampling switch closes, the source must charge the ADC's internal sampling capacitance to the required accuracy within the available acquisition time.

If the source impedance is too high, the input driver is too slow, or the acquisition window is too short, the sampled voltage may not settle sufficiently. This creates a conversion error even if the ADC itself has excellent DC specifications.

First-Order Settling Estimate

For a simple one-pole RC network responding to a worst-case full-scale step, the residual settling error falls exponentially:

Error fraction ≈ e^(-tACQ / RC)

To settle within approximately one-half LSB of an ideal N-bit converter, a useful first-order estimate is:

tACQ ≥ (N + 1) × ln(2) × R × C

≈ 0.693 × (N + 1) × R × C

This equation is only a starting point. A real SAR input network can include switch resistance, nonlinear capacitance, charge kickback, external RC filtering, amplifier output impedance, and device-specific acquisition behavior. Use the manufacturer's recommended driver circuit and settling method for the final design.

Capacitive DAC and Comparator

Many modern SAR ADCs use a capacitive DAC, also called a charge-redistribution DAC. The capacitor array can perform both sampling and code-dependent charge redistribution. This allows the comparator to evaluate each trial without requiring a separate resistor-string DAC.

However, not every SAR ADC uses the same internal implementation. Designers should treat the block diagram as a functional model and use the actual datasheet when calculating input drive, common-mode behavior, reference loading, and timing.

Why the Voltage Reference Matters

The reference is not just a static voltage label. In many precision SAR ADCs, internal capacitor switching causes a dynamic current demand at the reference input. A weak or noisy reference network can produce gain error, code-dependent errors, excess noise, or poor settling.

Check the following:

• reference accuracy and temperature drift;
• reference noise across the signal bandwidth;
• required reservoir or decoupling capacitor;
• reference-buffer drive capability and stability;
• reference settling after power-up or a large code transition;
• PCB placement and return-current path.

Resolution, LSB Size, and Real Accuracy

For an ideal N-bit ADC with an input span from Vmin to Vmax, the ideal code width is approximately:

Ideal LSB size = (Vmax - Vmin) / 2^N

For example, a 16-bit ADC covering 0 V to 5 V has an ideal LSB size of about 76.3 µV:

5 V / 65,536 ≈ 76.3 µV per LSB

That does not mean the complete system can make 76.3 µV accurate measurements. Real performance also depends on noise, ENOB, INL, DNL, offset, gain error, reference quality, input-driver settling, thermal effects, and PCB layout.

For a deeper look at resolution and sampling trade-offs, see 24bit ADC Selection Guide: Resolution, LSB, and Sampling Rate.

SAR ADC Strengths

SAR ADC Limits and Common Design Mistakes

SAR ADC vs Delta-Sigma vs Flash ADC

For more detail, see Delta-Sigma ADC Explained and Flash Analog to Digital Converter Explained.

When Should You Choose a SAR ADC?

A SAR ADC is often a strong candidate when the system requires several of the following at the same time:

• low conversion latency;
• deterministic sampling and conversion timing;
• moderate-to-high sample rate;
• good DC and AC precision;
• multiplexed input channels;
• reasonable power consumption;
• SPI or another straightforward digital interface;
• fast recovery after switching between channels.

Choose by the signal and system requirements rather than the architecture name alone. A delta-sigma ADC may be a better choice when maximum low-frequency precision is more important than latency. A flash ADC is more appropriate when conversion speed dominates the design.

SAR ADC Selection Checklist

Applications of SAR ADCs

• Industrial data acquisition: pressure, temperature, current, voltage, vibration, and process signals.
• Control systems: current loops, servo feedback, motor control, and power-conversion feedback where latency matters.
• Test and measurement: bench instruments, portable instruments, automated test equipment, and precision logging.
• Multiplexed sensor systems: several analog channels scanned by one converter.
• Battery-powered electronics: duty-cycled measurement and low-power acquisition.
• Embedded systems: external ADCs used when an MCU's integrated ADC does not meet accuracy, speed, channel, or input-range requirements.

Related ADC Guides

FAQ

What is a SAR ADC in simple terms?

A SAR ADC samples an analog voltage and determines its digital code one bit at a time. It uses an internal DAC, comparator, and successive approximation logic to narrow the possible result from the MSB to the LSB.

Is a SAR ADC always faster than a delta-sigma ADC?

No. SAR ADCs typically provide low conversion latency and are available at high throughput, but converter families overlap. Some delta-sigma ADCs can also operate at high output data rates. Compare usable bandwidth, latency, noise, and required precision rather than relying only on the architecture name.

Does an N-bit SAR ADC always need exactly N clock cycles?

The core binary-search algorithm makes N main bit decisions, but the complete device conversion time may include acquisition, internal clocking, calibration, settling, and data-interface cycles. Use the timing diagram in the specific datasheet.

Why can a high source impedance cause SAR ADC errors?

The SAR input often includes a switched sampling capacitance. A high source impedance can prevent this capacitance from settling to the input voltage within the acquisition window, which creates conversion error.

Does a higher-resolution SAR ADC automatically give better accuracy?

No. More bits reduce the ideal LSB size, but system accuracy also depends on noise, ENOB, INL, DNL, offset, gain error, the voltage reference, driver settling, layout, and temperature effects.

Can a sensor drive a SAR ADC directly?

Sometimes. Direct drive can work when the sensor or source has low enough impedance and the ADC has enough acquisition time to settle to the required error target. Otherwise, a suitable buffer amplifier or different RC network may be required.

References and Further Reading

• Analog Devices — Successive-Approximation ADCs: Ensuring a Valid First Conversion
• Analog Devices — Voltage Reference Design for Precision Successive-Approximation ADCs
• Texas Instruments — Driving a SAR ADC Directly Without a Front-End Buffer Circuit
• Texas Instruments — ADS8860 SAR ADC Product Information
• Analog Devices — AD4007 Precision SAR ADC Product Information

Technical note: ideal equations and examples in this guide explain the conversion principle. Production designs should use the electrical characteristics, timing diagrams, transfer-function definitions, and layout recommendations in the exact ADC datasheet.