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SAR ADC Explained: How Successive Approximation Converters Work
A SAR ADC converter, or successive approximation register analog-to-digital converter, converts an analog input voltage into a digital code by testing one bit at a time. Rather than measuring every possible code directly, the converter uses a binary search: try the midpoint, decide whether the input is higher or lower, then repeat with the next bit until it finds the final code.
As a result, the SAR ADC has become one of the most practical general-purpose ADC architectures. Engineers usually choose it when a design needs moderate to high resolution, deterministic conversion timing, low latency, and reasonable power consumption. You will often find SAR ADCs in sensor interfaces, industrial measurement, battery-powered devices, data acquisition systems, and microcontrollers with integrated ADCs.
| Question | Short Answer |
|---|---|
| What is a SAR ADC? | An ADC architecture that finds the digital output code through a bit-by-bit binary search |
| What does SAR mean? | Successive approximation register |
| What are the key internal blocks? | Sample-and-hold circuit, capacitive DAC, comparator, SAR logic, reference input |
| How many comparison steps are needed? | An N-bit SAR ADC normally needs N bit decisions for one conversion |
| When is SAR a good choice? | Low-latency, multiplexed, medium-to-high-resolution measurement where sample rate is not in the extreme flash range |
What Is a SAR ADC?
A SAR ADC is an analog-to-digital converter that uses a successive approximation register to determine the digital code representing an analog input. The word "successive" matters because the converter does not guess the whole result at once. Instead, it approximates the answer step by step, starting with the most significant bit (MSB), then moving toward the least significant bit (LSB).
For a 12-bit SAR ADC, that means 12 main bit decisions. A 16-bit SAR ADC, by comparison, needs 16 main bit decisions. Real devices add acquisition, settling, calibration, or interface timing, but the core conversion principle stays the same: one bit decision at a time.
How Does a Successive Approximation ADC Work?
A successive approximation ADC works by combining a sampled input voltage, an internal DAC, a comparator, and SAR control logic. First, the sample-and-hold circuit captures the input so the voltage does not move during conversion. Next, the DAC generates trial voltages that represent candidate digital codes. Finally, the comparator tells the SAR logic whether each trial is too high or too low.
- Sample-and-hold captures the input voltage.
- SAR logic sets the MSB to 1 and the other bits to 0.
- An internal DAC converts that trial code into an analog voltage.
- A comparator checks whether the held input is above or below the DAC voltage.
- If the input is higher, the SAR keeps the bit. If the input is lower, it clears the bit.
- SAR logic repeats the test for the next bit.
- After the LSB decision, the register contains the ADC output code.
Binary Search Conversion in a SAR ADC
Binary search is the core idea behind successive approximation. Imagine a 4-bit ADC with 16 possible output codes, from 0000 to 1111. The converter first tests the midpoint, then narrows the range by half with each comparison.
| Bit Trial | Trial Code | Meaning | Comparator Decision |
|---|---|---|---|
| MSB | 1000 | Test half scale | Keep if input is above half scale |
| Bit 2 | 1100 or 0100 | Test the midpoint of the remaining range | Keep or clear |
| Bit 1 | Smaller interval | Test again | Keep or clear |
| LSB | Smallest interval | Final code decision | Finish conversion |
With each bit, the converter cuts the possible answer range in half. That is why an N-bit SAR ADC scales cleanly with resolution: more bits mean more comparison decisions, but not an exponential increase in comparators.
Sample-and-Hold: Why the Input Must Stay Still
The binary search only works if the input voltage stays effectively constant during the conversion. During acquisition, the ADC input charges an internal sampling capacitor to the input voltage. During conversion, the ADC isolates that capacitor so the comparator can check the held voltage against DAC trial voltages.
| Design Point | Why It Matters |
|---|---|
| Source impedance | A high source impedance may not charge the sampling capacitor fully during acquisition |
| Acquisition time | The input needs enough time to settle before conversion begins |
| Input driver | Some SAR ADCs need an op amp or buffer to drive the switched-capacitor input |
| Multiplexing | After switching channels, the input may need extra settling time |
| Reference stability | The reference voltage sets the DAC trial levels and directly affects code accuracy |
Capacitive DAC and Comparator Inside a SAR ADC
Many modern SAR ADCs use a capacitive DAC, sometimes called a charge-redistribution DAC. Although the exact implementation varies by device, the purpose stays consistent: the DAC generates the analog trial voltage that the comparator checks against the sampled input.
| Block | Role in Conversion |
|---|---|
| Sample capacitor network | Captures and holds the input voltage |
| Capacitive DAC | Generates trial voltages for each bit decision |
| Comparator | Decides whether the sampled input is above or below the trial voltage |
| SAR logic | Sets, keeps, or clears each bit based on comparator output |
| Reference input | Defines the full-scale range and DAC step size |
| Digital interface | Sends the final code to the controller |
SAR ADC Strengths
| Strength | Practical Meaning |
|---|---|
| Low latency | A conversion result is available after a defined conversion cycle, without a long digital filter delay |
| Good resolution range | Common SAR devices cover many 8-bit to 18-bit design needs; higher-resolution SAR parts also exist |
| Efficient architecture | One comparator can be reused for bit decisions, avoiding the comparator explosion of flash ADCs |
| Multiplexer friendly | SAR ADCs can work well in systems that scan multiple input channels |
| Power scalability | Often attractive for portable, battery, and embedded systems |
SAR ADC Limits and Common Mistakes
| Mistake | Why It Causes Problems |
|---|---|
| Ignoring acquisition time | The sampled voltage may not settle to the real input before conversion starts |
| Driving the ADC directly from a weak sensor | The switched-capacitor input can disturb the sensor output |
| Treating reference voltage as an afterthought | Reference noise or droop appears directly in the conversion result |
| Choosing only by bit count | A 16-bit label does not guarantee 16 noise-free bits in the system |
| Multiplexing too quickly | The previous channel can affect the next channel if settling is insufficient |
SAR ADC vs Delta-Sigma vs Flash ADC
| Architecture | How It Works | Strengths | Limits | Typical Fit |
|---|---|---|---|---|
| SAR ADC | Samples input, runs a bit-by-bit binary search using a DAC and comparator | Low latency, efficient, good for multiplexed channels | Needs careful input settling and reference design | Sensor acquisition, control loops, industrial data acquisition |
| Delta-Sigma ADC | Oversamples the input, shapes noise, and uses digital filtering | High resolution for low-frequency precision measurement | Digital filter latency and lower bandwidth | Weigh scales, precision sensors, audio, slow measurement |
| Flash ADC | Uses many comparators in parallel | Extremely fast conversion | Comparator count, power, and resolution scaling limits | Very high-speed measurement, RF, radar, fast instrumentation |
When Should You Choose a SAR ADC?
Choose a SAR ADC when the design needs low conversion latency, multiplexed channel scanning, practical 8-bit to 18-bit class resolution, moderate to high sampling rates, and reasonable power. Consider delta-sigma when very high resolution at low bandwidth matters more than latency. Finally, consider flash when maximum speed dominates and power, cost, and resolution trade-offs are acceptable.
SAR ADC Selection Checklist
| Check | What to Confirm |
|---|---|
| Resolution | Required bits and required noise-free performance |
| Sampling rate | Samples per second per channel, not only total converter rate |
| Number of channels | Single-channel, simultaneous sampling, or multiplexed input |
| Input type | Single-ended, pseudo-differential, or fully differential |
| Input range | Unipolar, bipolar, rail-to-rail, or reference-scaled input |
| Reference | Accuracy, drift, noise, drive capability, and layout |
| Availability and compliance | 库存、价格、交期、认证、生命周期：知识库未明确 |
FAQ
What is a SAR ADC in simple terms?
A SAR ADC converts an analog input into a digital code by testing one bit at a time. It starts with the largest bit, compares the input against a DAC-generated trial voltage, then keeps or clears each bit until the final code is complete.
How does a successive approximation ADC work?
It samples the input, holds the voltage steady, uses an internal DAC to generate trial voltages, and uses a comparator to decide whether each trial code is too high or too low. The successive approximation register records those decisions as the output code.
Is a SAR ADC better than a delta-sigma ADC?
Not always. SAR is usually better for low latency, multiplexed inputs, and many embedded measurements. By contrast, delta-sigma is usually better for very high-resolution, low-frequency precision measurement where digital filter latency is acceptable.
Alice lee
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